Microcomputers are widely used in paging receivers and a number of other radio frequency (RF) communication devices. Because, in recent years, paging receivers have begun to include a greater number of features, such as alphanumeric displays and real time clocks, complex circuitry has been added to support the additional operations. At the same time, however, paging receivers have become smaller. Therefore, the additional circuitry, which is sometimes very complex, is often integrated and included in microcomputers, resulting in larger, less efficient microcomputers which cannot be implemented in a cost effective manner.
One approach to solving this problem is to use an expanded microcomputer system in which circuits including a processing unit, a random access memory (RAM), a read only memory (ROM), programmable elements, etc. are implemented on more than one chip. For instance, a first chip, e.g., a master microcomputer, can have included therein a central processing unit, memory, and various other processing elements, while a second chip, e.g., a slave microcomputer or other type of expansion chip, can be used to incorporate additional processing elements, such as expanded ROM. The two chips are inter-connected by a communication bus which allows two-way communication therebetween. This solution, however, is often not feasible for use in RF communication devices, such as paging receivers, because the communication bus often generates intense RF interference that interferes with the operation of the receiver. This interference is often so severe that information transmitted to the paging receiver can be erroneously received or entirely missed.
Thus, what is needed is a method and apparatus for controlling RF interference in an expanded microcomputer system having one or more chips inter-connected to a microcomputer by a communication bus.